 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| XX-XXXX; Rev 0; 5/02 3V 10-Tap Silicon Delay Line General Description The DS1110L 10-tap delay line is a 3V version of the DS1110. It has 10 equally spaced taps providing delays from 10ns to 500ns. The DS1110L series delay lines provide a nominal accuracy of 5% or 2ns, whichever is greater, at 3.3V and +25C. The DS1110L is characterized to operate from 2.7V to 3.6V. The DS1110L produces both leading- and trailing-edge delays with equal precision. The device is offered in a standard 14-pin TSSOP. All-Silicon Delay Line 3V Version of the DS1110 10 Taps Equally Spaced Delays Are Stable and Precise Leading- and Trailing-Edge Accuracy Delay Tolerance 5% or 2ns, Whichever Is Greater, at 3.3V and +25C Economical Low-Profile 14-Pin TSSOP Low-Power CMOS TTL/CMOS Compatible Vapor Phase and IR Solderable Fast-Turn Prototypes Delays Specified Over Commercial and Industrial Temperature Ranges Custom Delays Available Features DS1110L Applications Communications Equipment Medical Devices Automated Test Equipment PC Peripheral Devices Pin Configuration PART Ordering Information TEMP RANGE -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C PINPACKAGE 14 TSSOP (173mil) 14 TSSOP (173mil) 14 TSSOP (173mil) 14 TSSOP (173mil) 14 TSSOP (173mil) 14 TSSOP (173mil) 14 TSSOP (173mil) 14 TSSOP (173mil) 14 TSSOP (173mil) 14 TSSOP (173mil) 14 TSSOP (173mil) TOTAL DELAY (ns) * 100 125 150 175 200 250 300 350 400 450 500 TOP VIEW IN 1 N.C. TAP2 2 3 14 VCC 13 TAP1 DS1110LE-100 DS1110LE-125 DS1110LE-150 DS1110LE-175 DS1110LE-200 DS1110LE-250 DS1110LE-300 DS1110LE-350 DS1110LE-400 DS1110LE-450 DS1110LE-500 DS1110L 12 TAP3 11 TAP5 10 TAP7 9 8 TAP9 TAP10 TAP4 4 TAP6 5 TAP8 6 GND 7 TSSOP (173mil) *Custom delays are available. _____________________________________________ Maxim Integrated Products 1 For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com. 3V 10-Tap Silicon Delay Line DS1110L ABSOLUTE MAXIMUM RATINGS Voltage on Any Pin Relative to Ground .................-0.5V to +6.0V Operating Temperature Range ...........................-40C to +85C Storage Temperature Range .............................-55C to +125C Soldering Temperature...................See IPC/JEDEC J-STD-020A Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC ELECTRICAL CHARACTERISTICS (-40C to +85C, VCC = 2.7V to 3.6V.) PARAMETER Supply Voltage High-Level Input Voltage Low-Level Input Voltage Input Leakage Current Active Current High-Level Output Current Low-Level Output Current SYMBOL VCC VIH VIL II ICC IOH IOL (Note 1) (Note 1) (Note 1) 0V VI VCC VCC = max, period = min (Note 2) VCC = min, VOH = 2.3V VCC = min, VOL = 0.5V 12 CONDITIONS MIN 2.7 2.2 -0.3 -1.0 40 TYP 3.3 MAX 3.6 VCC + 0.3 +0.8 +1.0 150 -1.0 UNITS V V V A mA mA mA AC ELECTRICAL CHARACTERISTICS (-40C to +85C, VCC = 2.7V to 3.6V.) PARAMETER Input Pulse Width Input to Tap Delay (Delays 40ns) Input to Tap Delay (Delays > 40ns) Power-Up Time Input Period SYMBOL tWI tPLH tPHL tPLH tPHL tPU Period (Note 8) 2 (tWI) (Note 6) +25C, 3.3V (Notes 3, 5, 6, 7) 0C to +70C (Notes 4-7) -40C to +85C (Notes 4-7) +25C, 3.3V (Notes 3, 5, 6, 7) 0C to +70C (Notes 4-7) -40C to +85C (Notes 4-7) CONDITIONS MIN 10% of tap 10 -2 -3 -4 -5 -8 -13 Table 1 Table 1 Table 1 Table 1 Table 1 Table 1 +2 +3 +4 +5 +8 +13 100 ms ns % ns TYP MAX UNITS ns 2 ______________________________________________________________________ 3V 10-Tap Silicon Delay Line CAPACITANCE (TA = +25C.) PARAMETER Input Capacitance SYMBOL CIN CONDITIONS MIN TYP 5 MAX 10 UNITS pF DS1110L Note 1: Note 2: Note 3: Note 4: Note 5: Note 6: Note 7: Note 8: All voltages are referenced to ground. Measured with outputs open. Initial tolerances are with respect to the nominal value at +25C and VCC = 3.3V for both leading and trailing edges. Temperature and voltage tolerances are with respect to the nominal delay value over stated temperature range and a 2.7V to 3.6V range. Intermediate delay values are available on a custom basis. See Test Conditions section. All tap delays tend to vary unidirectionally with temperature or voltage changes. For example, if tap 1 slows down, all other taps also slow down; tap 3 can never be faster than tap 2. Pulse width and period specifications may be exceeded; however, accuracy is application sensitive (decoupling, layout, etc.). Typical Operating Characteristics (VCC = 3.3V, TA = +25C, unless otherwise noted.) DELAY CHANGE (%) vs. VCC DS1110L-500 DS1110L toc01 DELAY CHANGE (%) vs. VCC DS1110L-250 0.2 CHANGE IN DELAY (%) 0.1 0 -0.1 -0.2 -0.3 -0.4 RAISING EDGE FALLING EDGE DS1110L toc02 0.10 0.05 CHANGE IN DELAY (%) 0 -0.05 -0.10 -0.15 -0.20 -0.25 -0.30 -0.35 2.7 3.0 VCC (V) 3.3 RAISING EDGE FALLING EDGE 0.3 3.6 2.7 3.0 VCC (V) 3.3 3.6 CHANGE IN DELAY (%) vs. TEMPERATURE DS1110L-500 DS1110L toc03 CHANGE IN DELAY (%) vs. TEMPERATURE DS1110L-250 DS1110L toc04 6 5 4 CHANGE IN DELAY (%) 3 2 1 0 -1 -2 -3 -4 -5 -40 -15 10 35 60 RISING EDGE FALLING EDGE 4 3 CHANGE IN DELAY (%) 2 1 0 -1 -2 -3 RISING EDGE FALLING EDGE 85 -40 -15 10 35 60 85 TEMPERATURE (C) TEMPERATURE (C) _____________________________________________________________________ 3 3V 10-Tap Silicon Delay Line DS1110L Typical Operating Characteristics (continued) (VCC = 3.3V, TA = +25C, unless otherwise noted.) OUTPUT CURRENT HIGH vs. OUTPUT VOLTAGE HIGH DS1110L toc05 OUTPUT CURRENT LOW vs. OUTPUT VOLTAGE LOW 1.60E-02 OUTPUT CURRENT LOW (A) 1.40E-02 1.20E-02 1.00E-02 8.00E-03 6.00E-03 4.00E-03 2.00E-03 0.00E+00 VCC = 2.7V DS1110L toc06 0.00E+0 -2.00E-03 OUTPUT CURRENT HIGH (A) -4.00E-03 -6.00E-03 -8.00E-03 -1.00E-02 -1.20E-02 -1.40E-02 -1.60E-02 -1.80E-02 2.0 2.1 2.2 2.3 2.4 2.5 2.6 VCC = 2.7V 1.80E-02 2.7 0 0.1 0.2 0.3 0.4 0.5 0.6 OUTPUT VOLTAGE HIGH (V) OUTPUT VOLTAGE LOW (V) ACTIVE CURRENT vs. INPUT FREQUENCY DS1110L-250 45 40 35 CURRENT (mA) 30 25 20 15 10 5 0 0.1 1 10 100 FREQUENCY (MHz) VCC = 3.6V 15pF LOAD ON EACH TAP 5 DS1110L toc07 ACTIVE CURRENT vs. INPUT FREQUENCY DS1110L-500 DS1110L toc08 50 25 20 CURRENT (mA) 15 10 VCC = 3.6V 15pF LOAD ON EACH TAP 0.1 1.0 FREQUENCY (MHz) 10 0 Pin Description PIN 1 2 7 13, 3, 12, 4, 11, 5, 10, 6, 9, 8 14 NAME IN N.C. GND Tap 1-Tap 10 VCC Input No Connection Ground Tap Output Number 2.7V to 3.6V FUNCTION 4 ______________________________________________________________________ 3V 10-Tap Silicon Delay Line Detailed Description The DS1110L 10-tap delay line is a 3V version of the DS1110. It has 10 equally spaced taps providing delays from 10ns to 500ns. The device is offered in a standard 14-pin TSSOP. The DS1110L series delay lines provide a nominal accuracy of 5% or 2ns, whichever is greater, at 3.3V and +25C. The DS1110L is characterized to operate from 2.7V to 3.6V. The DS1110L reproduces the input-logic state at the tap 10 output after a fixed delay as specified by the dash-number suffix of the part number (Table 1). The DS1110L produces both leading- and trailing-edge delays with equal precision. Each tap is capable of driving up to 10 74LS-type loads. Dallas Semiconductor can customize standard products to meet specific needs. Figure 1 is the DS1110_L logic diagram and Figure 2 shows the timing diagram for the silicon delay line. DS1110L Table 1. Part Number by Delay (tPHL, tPLH) PART DS1110LE-100 DS1110LE-125 DS1110LE-150 DS1110LE-175 DS1110LE-200 DS1110LE-250 DS1110LE-300 DS1110LE-350 DS1110LE-400 DS1110LE-450 DS1110LE-500 TOTAL DELAY (ns) 100 125 150 175 200 250 300 350 400 450 500 DELAY/TAP (ns) 10 12.5 15 17.5 20 25 30 35 40 45 50 TAP1 TAP2 TAP9 TAP10 IN 10% 10% 10% 10% Figure 1. Logic Diagram PERIOD tRISE tFALL VIH 2.4V 1.5V 0.6V 2.4V 1.5V 0.6V 1.5V IN VIL tWI tWI tPLH tPLH 1.5V OUT 1.5V Figure 2. Timing Diagram: Silicon Delay Line _____________________________________________________________________ 5 3V 10-Tap Silicon Delay Line DS1110L Terminology Period: The time elapsed between the leading edge of the first pulse and the leading edge of the following pulse. t WI (Pulse Width): The elapsed time on the pulse between the 1.5V point on the leading edge and the 1.5V point on the trailing edge, or the 1.5V point on the trailing edge and the 1.5V point on the leading edge. tRISE (Input Rise Time): The elapsed time between the 20% and the 80% point on the leading edge of the input pulse. tFALL (Input Fall Time): The elapsed time between the 80% and the 20% point on the trailing edge of the input pulse. tPLH (Time Delay Rising): The elapsed time between the 1.5V point on the leading edge of the input pulse and the 1.5V point on the leading edge of any tap output pulse. tPHL (Time Delay, Falling): The elapsed time between the 1.5V point on the trailing edge of the input pulse and the 1.5V point on the trailing edge of any tap output pulse. Test Setup Description Figure 3 illustrates the hardware configuration used for measuring the timing parameters on the DS1110L. A precision pulse generator under software control produces the input waveform. Time delays are measured by a time interval counter (20ps resolution) connected PULSE GENERATOR START Z0 = 50 TIME INTERVAL COUNTER STOP VHF SWITCH CONTROL UNIT DEVICE UNDER TEST Figure 3. Test Circuit 6 ______________________________________________________________________ 3V 10-Tap Silicon Delay Line between the input and each tap. Each tap is selected and connected to the counter by a VHF switch-control unit. All measurements are fully automated, with each instrument controlled by a central computer over an IEEE-488 bus. Chip Information TRANSISTOR COUNT: 6813 DS1110L Output Each output is loaded with the equivalent of one 450 resistor in parallel with a 15pF capacitor. Delay is measured at the 1.5V level on the rising and falling edge. Package Information For the latest package outline information, go to www.maxim-ic. com/packages. Table 2. Test Conditions INPUT Ambient Temperature Supply Voltage (VCC) Input Pulse Source Impedance Rise and Fall Time Pulse Width Period 3.3V 0.1V High = 3.0V 0.1V Low = 0.0V 0.1V 50 max 2ns max 500ns (1s for - 500ns) 1s (2s for - 500ns) CONDITION +25C 3C Note: Above conditions are for test only and do not restrict the operation of the device under other data sheet conditions. Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 _____________________ 7 (c) 2002 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products. |
Price & Availability of DS1110L
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |